(a) Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a method of manufacturing a semiconductor device including a plurality of MOS transistors that are separately formed in levels of a structure having height differences.
(b) Description of the Related Art
Since semiconductor devices have been highly integrated, a plurality of MOS transistors have been formed on a single wafer. Such MOS transistors are separated by an isolation layer, and such an isolation layer may be formed by using a shallow trench insulation (STI) or local oxidation of silicon (LOCOS) structure.
FIG. 1 is a cross-sectional view showing a conventional method of forming a plurality of MOS transistors on a semiconductor device.
As shown in FIG. 1, three MOS transistors 20, 30, and 40 are formed on a substrate 10, and STI structures 13 and 15 are formed between each transistor.
In order to form the STI structures 13 and 15, a nitride layer (not shown) and a resist are firstly formed on the substrate 10, and then the resist is patterned. The nitride layer is dry-etched by using the patterned resist as an etch mask, and then the substrate 10 is etched by using the etched nitride layer as an etch mask. After depositing an oxide layer on such a trench and an entire surface of the substrate 10, the STI structures 13 and 15 are finally formed by removing the oxide layer and nitride layer on the surface of the substrate through a chemical mechanical polishing (CMP) process.
Consequently, device isolation regions are separated from active regions in which MOS transistors will be formed.
Thereafter, MOS transistors 20, 30, and 40 are formed by performing a general formation process of a MOS transistor.
However, when transistors are separated by using an STI structure, an additional device isolation region is required to form the STI structure. In addition, as shown in FIG. 1, a moat A can be created at edges of the STI structures 13 and 15 during a CMP process for forming the STI structures 13 and 15.
Such a moat may induce a hump phenomenon and an inverse narrow width effect (INWE) in a semiconductor device, and it may induce an abnormal operation of a semiconductor device. Therefore, higher integration of a semiconductor device cannot be easily accomplished because additional spaces are necessary for insulating such a moat, and manufacturing costs can be increased because additional processes are required for insulating such a moat.
The above information described in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form prior art with respect to the present invention.